1. Field of the Invention
Embodiments of the invention relate to operational amplifier circuits with a wide range of common mode input voltages and a decreased offset voltages.
2. Description of the Related Art
With a recent trends of single polarity of driving power supplies and decreased power supply voltage Vdd, operational amplifier circuits of a rail-to-rail input type are drawing attention in which an input voltage range is expanded over nearly power supply voltage width of GND to Vdd. For instance, a differential input circuit, which is a MOS differential pair composed of MOS-FETs, is connected in parallel with a cascode amplifier circuit to enhance a gain. Current imbalance between the MOS-FETs of the MOS differential pair is trimmed to cancel the offset voltage between the MOS differential pairs.
FIG. 3 shows an example of schematic construction of a conventional operational amplifier circuit of a P-MOS input folded cascode type provided with an offset voltage trimming circuit. The operational amplifier circuit of FIG. 3 includes a P-MOS differential pair A for differentially amplifying an common mode input voltage given to a pair of voltage input terminals INP and INM, and a current source B for biasing the P-MOS differential pair A. The P-MOS differential pair A is composed of a pair of MOS-FETs of a P channel type (hereinafter referred to simply as a P-MOS) 1a and 1b. The bias current source B is composed of a grounded-gate P-MOS 2.
The cascode circuit C of an input folded type for the P-MOS differential pair A is composed of an N-MOS cascode amplification stage and a P-MOS cascode amplification stage. The N-MOS cascode amplification stage consists of an N channel type MOS-FET (hereinafter referred to as an N-MOS) 3a, the source of which is connected to the drain of the P-MOS 1a, and an N-MOS 3b, the source of which is connected to the drain of the P-MOS 1b. The P-MOS cascode amplification stage consists of a pair of P-MOS 4a and P-MOS 4b that are cascode-connected to the respective drains of the N-MOS 3a and the N-MOS 3b. A pair of P-MOS 5a and P-MOS 5b forming a current mirror circuit are connected to the sources of the P-MOS 4a and the P-MOS 4b and works as a load on the P-MOS cascode amplification stage. This pair of P-MOSes 5a and 5b is an active load D acting through the cascode circuit C on the P-MOS differential pair A. The cascode circuit C connected in series to the active load D forms a grounded-gate amplifier circuit and increases the output resistance to enhance the gain of the operational amplifier.
N-MOSes 6a through 6f are provided in parallel with each other and connected through a switching circuit E to the drains of the P-MOSes 1a and 1b and the sources of the N-MOSes 3a and 3b. The N-MOSes 6a through 6f are loads on the N-MOS cascode amplification stage consisting of the N-MOSes 3a and 3b, and at the same time, construct a current source F for the P-MOS differential pair A and the cascode circuit C. The switching circuit E comprises switches 7a through 7f each series-connected to each drain of the N-MOSes 6a through 6f. These switches 7a through 7f performs selective ON/OFF operation and connect the P-MOS differential pair A and the cascode circuit C selectively to the current source F. Consequently, the switching circuit E and the current source F adjust the current to be drawn out of each of the P-MOSes 1a and 1b composing the MOS differential pair A. Thus, the switching circuit E and the current source F work as an offset voltage adjusting circuit, or a current trimming circuit, that corrects or trims the current imbalance between the P-MOS 1a and the P-MOS 1b. 
When non-uniformity exists in characteristics between the P-MOSes 1a and 1b composing the P-MOS differential pair A or between the P-MOSes 5a and 5b composing the active load D, the non-uniformity causes imbalance between the current running through the P-MOS 1a and the current through the P-MOS 1b. This current imbalance changes the output voltage, which in turn is fed back to the P-MOS differential pair A so as to compensate for the current imbalance. As a result, the voltages applied to the P-MOSes 1a and 1b differs from each other and settles into the state the current imbalance has disappeared.
In this state, the difference in the voltage on the P-MOS 1a and on the P-MOS 1b is superimposed on the output voltage as an offset voltage. The current adjustment by the switching circuit E corrects, or trims, the current imbalance between the P-MOSes 1a and 1b to cancel this offset voltage. International Patent Application Publication No. WO 2007/002944 discloses techniques for trimming the offset voltage in an operational amplifier in detail.
FIG. 4 shows an example of schematic construction of a conventional operational amplifier circuit of a rail-to-rail input folded-cascode type. This operational amplifier circuit comprises, in addition to the operational amplifier having the construction shown in FIG. 3, an N-MOS differential pair G consisting of a pair of N-MOS-FETs 8a and 8b provided in parallel with the P-MOS differential pair A. The drains of the N-MOS-FETs 8a and 8b are connected to the corresponding sources of the pair of P-MOSes 4a and 4b in the cascode circuit C. The operational amplifier of FIG. 4 comprises a current source H for biasing the N-MOS differential pair G and is composed of a grounded gate N-MOS 9.
The operational amplifier shown in FIG. 4 is not provided with the current trimming circuit, a switching circuit E, for offset voltage regulation of the P-MOS differential pair A and the N-MOS differential pair G. Thus, the current source Fa for the P-MOS differential pair A is solely composed of the pair of N-MOSes 6a and 6b, and the operational amplifier circuit is not provided with the N-MOSes 6c through 6f used for adjusting current imbalance in the circuit of FIG. 3. In this operational amplifier circuit of FIG. 4, the active load D, P-MOSes 5a and 5b, on the P-MOS differential pair A functions as a current source for the N-MOS differential pair G, and the current source Fa, the N-MOSes 6a and 6b, for the P-MOS differential pair A functions as an active load on the N-MOS differential pair G.
In the operational amplifier circuit provided with the P-MOS differential pair A and the N-MOS differential pair G, either one of the P-MOS differential pair A and the N-MOS differential pair G operates normally in the input voltage range of the ground potential GND to the power supply voltage Vdd. Since an input voltage range of approximately the power supply voltage width, from GND to Vdd is obtained, the operational amplifier circuit is called a rail-to-rail input type operational amplifier circuit.
Kenji Taniguchi: “Introduction to CMOS Analogue Circuits for LSI Design” (in Japanese) First edition, published by CQ Publishing Co. Ltd., December 2004, pages 200-204. in detail about an operational amplifier circuit of a rail-to-rail input type.
In the operational amplifier circuit of a rail-to-rail type as shown in FIG. 4, if the current running through the P-MOS differential pair A, the P-MOSes 1 and 1b, is trimmed, for example, by the current source F provided in the operational amplifier circuit of FIG. 3, an offset voltage arises in the N-MOS differential pair G, the N-MOSes 8a and 8b. If the offset voltage in the N-MOS differential pair G, N-MOSes 8a and 8b, is cancelled, then an offset voltage arises in the P-MOS differential pair A, P-MOSes 1a and 1b. Thus, it is impossible to simultaneously cancel the offset voltage in the P-MOS differential pair A, P-MOSes 1a and 1b, and the offset voltage in the N-MOS differential pair G, N-MOSes 8a and 8b. 